The present invention generally relates to computer architecture, and more specifically, to simplified sparing and recovery options for processors or cores in multi-core systems.
Computer system manufacturers and computer processor manufacturers continually strive to produce faster and more reliable computer systems. One way that computer systems are made faster and more reliable is to provide a multi-processing computer system. A multi-processing computer system can be implemented using multiple single-core processors or one or more multi-core processors. A multiprocessing computer system can be faster than a single processor system because the multiple processor cores can be made to execute tasks in parallel with one another. A multi-processing computer system can be made more reliable because, in the event of a failure of one processor or core, another processor or core can take over the functions that were being executed on the failed processor or core at the time of the failure. The capability to move an architectural state from one processor core of a multiprocessor computer system to another processor core can be referred to as processor sparing. In the existing art, sparing has been a complex process because the architectural state of the processor may be spread across multiple locations, including a mapper and a recovery buffer. In these cases, the sparing process must access both the mapper and the recovery buffer and process that information.
In addition to sparing is the related concept of recovery. While sparing involves replacing a processor core with a spare processor core, recovery involves stopping a processor core from executing, then restoring the processor from a known state, thus preserving the architecture. This recovery process includes moving information from a recovery buffer into a mapper and then performing a recovery reset that resets all non-architectural state to a known good reset state. There can be issues when mixing recovery with sparing.